Electronics systems can typically include a data storage capability. For example, bi-stable circuits, such as flip-flops can maintain a data value in one of two binary logic values depending upon a stored data value. One commonly used bi-stable circuit that can maintain a logic value until another value is written or rewritten is a latch.
A latch can take a number of different forms. For example, a latch can include cross-coupled inverters that can latch a data value on complementary data nodes until a new data value is rewritten. Such latches are often used as static random access memory (SRAM) cells. An SRAM type latch can store true and complementary logic values. Such stored data values can be read when an execution unit fetches data from an addressed storage cell, as but one example.
While an SRAM type latch can retain stored data without requiring refresh operations (is a “static” store), such a latch will lose a stored data value in the absence of power. However, there are many applications in which it is desirable for a data value to be retained even in the absence of power. Thus, many conventional applications include both a volatile storage circuit and a nonvolatile storage circuit.
While some systems may include nonvolatile storage circuits in an entirely different integrated circuit than volatile storage circuits, there may be instances where both volatile and nonvolatile storage elements are included in the same integrated circuit. In particular, it may be desirable to utilize a storage device having both volatile and nonvolatile features for the same data value. For example, if data is to be temporarily held while power is present, a storage device can utilize a latch into which data can be loaded and thereafter read. However, if the data stored is of sufficient importance, the data could be maintained after power is removed by storing the data value into a nonvolatile storage element. Such a desired storage device could function essentially as a latch, but also include nonvolatile storage for latched data. Such a circuit can be considered a “programmable” latch.
A conventional programmable latch is set forth in FIG. 9 in a schematic diagram and designated by the general reference character 900. A programmable latch 900 can include a volatile latch section 902, a multiplexer section 904, and a nonvolatile storage section 906. A conventional programmable latch 900 can be “one-time” programmable (OTP). That is, the programmable latch 900 can utilize nonvolatile storage elements that can be programmed but once (OTP devices). In the very particular example of FIG. 9, a nonvolatile storage section 906 can include anti-fuse devices 908-0 and 908-1.
To program one data value for the latch (e.g. logic “1”), one anti-fuse device (e.g., 908-1) can be programmed while the other anti-fuse (e.g., 908-0) can remain unprogrammed. To program another data value for the latch (e.g. logic “0”), the states of the anti-fuse devices can be reversed (e.g., 908-1 not programmed and 908-0 programmed).
In the particular example of FIG. 9, a conventional programmable latch 900 can include a program path for anti-fuse device 908-0 formed by n-channel transistors N95 and N93 (to ground) as enabled by transistor N91. Similarly, a program path for anti-fuse device 908-1 can be formed by n-channel transistors N94 and N92 (to ground) as enabled by transistor N90. A particular anti-fuse device (908-0 or 908-1) can be selected for programming according to a data value written into volatile latch section 902 (data latched at nodes D and DB).
Once a data value has been programmed, it can be recalled (i.e., loaded) back into volatile latch section 902. Based on the difference in current draw between the differently programmed anti-fuse devices (908-1 and 908-0), nodes D and DB can be driven to different potentials. The volatile latch section 902 can be configured to latch this programmed data value.
In the particular example of FIG. 9, a conventional programmable latch can include a data load path from anti-fuse device 908-0 formed by n-channel transistors N95 and N97, while a data load path for anti-fuse device 908-1 can be formed by n-channel transistors N94 and N96.
A drawback to the above conventional approach is that data load operations at lower voltages may not be reliably sensed. Lower voltage operations can include power-on reset (POR) operations. In addition, such a conventional programmable latch provides no way of testing anti-fuse devices individually, only testing the overall circuit according to data read and write operations. Still further, during programming operations, when an anti-fuse device is “blown” (changed from non-conductive to conductive) there can be a sudden inrush of current that can damage circuit components.